1. Field of the Invention
The present invention relates to a semiconductor memory device, which is used, for example, in a semiconductor chip on which a NAND type flash memory is mounted.
2. Description of the Related Art
Conventionally, nonvolatile memories, which are called “NAND type flash memories”, have been used and marketed (see, for instance, Jpn. Pat. Appln. KOKAI Publication No. 2002-016154 and Jpn. Pat. Appln. KOKAI Publication No. 2004-228323).
NAND type flash memories include a two-Level Cell NAND type flash memory, in which 1-bit data can be recorded in one memory cell. Further, NAND type flash memories include a Multi-Level Cell NAND type flash memory, in which a plurality of data can be recorded in one memory cell. Since the Multi-Level Cell NAND type flash memory can record a plurality of data in an area of one memory cell, it is possible to realize double or more the capacity of the two-Level Cell NAND type flash memory having the same area. Thus, with a recent increase in capacity of flash memories, attention has been paid to the Multi-Level Cell NAND type flash memory from the standpoint of reduction in chip area and cost.
However, the Multi-Level Cell NAND type flash memory, compared to the two-Level Cell NAND type flash memory, has the following restrictions 1 to 3 in use:
1. The data write time and data erase time are longer.
There is the following problem. At present, in the Multi-Level Cell NAND type flash memory, the time for writing data in cells is about three times longer than the time for writing data in cells in the two-Level Cell NAND type flash memory. In addition, at present, in the Multi-Level Cell NAND type flash memory, the time for erasing data in cells is about two times longer than the time for erasing data in cells in the two-Level Cell NAND type flash memory.
2. A higher data error correction performance is required.
The two-Level Cell NAND type flash memory is required to have a performance of correcting a 1-bit data error per 512-byte data. On the other hand, the Multi-Level Cell NAND type flash memory is required to have a performance of correcting 4-bit data errors per 512-byte data.
3. The number of executable rewrite operations decreases.
In the two-Level Cell NAND type flash memory, about 100,000 rewrite operations can be executed. In the Multi-Level Cell NAND type flash memory, about 10,000 rewrite operations are possible.
In the NAND type flash memory, in order to avoid concentration of data write in a given memory cell, a technique for dispersing write operations among cells (“Wear Leveling”) has been adopted. However, compared to the two-Level Cell NAND type flash memory, higher-level technology is needed to use the Multi-Level Cell NAND type flash memory. Hence, a greater deal of time and cost is required in developing programs, etc. therefor.
In the case where the NAND type flash memory is used as a memory medium, control means needs to be provided for adding an error correction code (ECC) at the time of data input/output control, data management and data write, and for analyzing/processing the error correction code (ECC) at the time of reading out data. In the ordinary Multi-Level Cell NAND type flash memory, such control means is not mounted in the same package. Thus, the user is required to prepare the control means separately.
On the other hand, since there are the above-described restrictions 1, 2 and 3 in use of the Multi-Level Cell NAND type flash memory, a certain level of technology, which can avoid the restrictions 1, 2 and 3 in use, is needed in order to provide the control means.